1. Field of the Invention
The present invention relates generally to semiconductor fabrication processes and, more particularly, a semiconductor fabrication method for eliminating inverse narrow width effects in dynamic random access memory (DRAM) devices.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. Typically, a trench-storage capacitor consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic planar view showing the layout of a prior art trench capacitor DRAM unit 1. FIG. 2 is an oblique cross-sectional view along line A′ of FIG. 1. As shown in FIG. 1, the trench capacitor DRAM unit 1 comprises an access transistor 2 formed on an active area (AA) 10, and a trench capacitor 3 electrically connected to one terminal of the access transistor 2. The active area 10 such as a P-type silicon substrate is isolated by shallow trench isolation (STI) region 20. The access transistor 2 comprises a gate conductor (GC) 12, an N-type doped source 101, and an N-type doped drain 102. The N-type doped source 101 and the N-type doped drain 102 define a channel region 103, as indicated in dark area. The channel region 103 has a channel length “L” and a channel width “W”. The N-type doped source 101 of the access transistor 2 is electrically connected to a bit line (not shown) through a contact 18. The N-type doped drain 102 of the access transistor 2 is electrically connected to a storage node (not shown) of the trench capacitor 3. As indicated in FIG. 2, a gate insulator 13 is disposed between the polysilicon gate 12 and the substrate 10.
There are several problems with the above-described prior art DRAM unit 1 as the dimension, either in channel length aspect or width aspect, of the DRAM cell shrinks to nano scale. As for channel length aspect, it is well known that short channel effects occur and a number of approaches have been addressed to solve such effects. However, as for shrunk channel width of the transistor, which results in problems such as STI corner effects, so-called inverse narrow width effects, and sub-threshold voltage leakage caused by sub-threshold voltage drop, there are few solutions for solving these problems, and thus becoming a bottleneck of further miniaturization of DRAM devices.